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Rockchip DDR DQ Eye Tool Guide

ID: RK-YH-YF-167

Release Version: V1.0.0

Date: 2021-03-05

Security Level: □Top-Secret □Secret □Internal ■Public

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Preface

Overview

The Rockchip DDR DQ Eye Tool provides the ability to view read/write eye diagrams for each DQ by entering commands under U-Boot.

Product Versions

Chip NameSoftware Version
RV1126U-Boot 2017.09
RK356xU-Boot 2017.09

Intended Audience

This document (this guide) is primarily intended for the following engineers:

Hardware Engineers

Technical Support Engineers

Software Development Engineers

Revision History

VersionAuthorDateDescription
V1.0.0Yao Xuwei2021-03-05Initial version

Table of Contents

[TOC]


Usage​

Preparation​

  1. Before building the U-Boot project, open menuconfig in the project root directory, go to Command line interface, configure Enable ddr test tool and save the build configuration (the Rockchip DDR DQ Eye Tool is integrated in the DDR Test Tool).

    Enable_ddr_test_tool

  2. Build the U-Boot project and flash the Loader and uboot (refer to the "Build and Flash" related chapters in the UBOOT documentation).

  3. Flash the Loader and uboot that support the DDR DQ Eye Tool (for RV1126 platform, you can flash the Loader packaged by the U-Boot project; for RK356x platform, please flash the Loader provided by Rockchip that supports this feature).

  4. Connect the serial port of the board under test to the host PC, ensuring normal serial communication between the board and the host. When the board boots, the host should hold Ctrl + C to stop the board at U-Boot (the appearance of "<INTERRUPT>" indicates the board has stopped at U-Boot).

    U-Boot_INTERRUPT

Viewing DDR DQ Read/Write Eye Diagram Under U-Boot​

Enter the command under U-Boot:

ddr_dq_eye <DDR frequency in MHz>

The parameter <DDR frequency in MHz> specifies the DDR clock frequency for which to view the DQ eye diagram, in MHz. When left blank, the default is the maximum frequency.

  • Example: To view the DQ eye diagram at DDR clock frequency of 1056MHz, enter the command under U-Boot:

    ddr_dq_eye 1056
  • Example: To view the DQ eye diagram at the maximum DDR clock frequency, enter the command under U-Boot:

    ddr_dq_eye

Output Result Analysis​

ddr_dq_eye_read

ddr_dq_eye_write

  • The tool first outputs tool version, DDR type, frequency, and other information.
  • The tool outputs read eye diagrams and write eye diagrams for each CS separately.
  • In the eye diagram output, positions marked with "-" are outside the eye, positions marked with "*" are inside the eye, and positions marked with "|" are sampling points.
  • The right side of the eye diagram shows the margins from the sampling point to the left and right boundaries of the eye (Margin_L, Margin_R), the sampling point position (Sample), eye width (Width), and other information. Eye widths marked in square brackets do not meet the minimum eye width limit (as shown for read eye diagram DQ0 in the figure).
  • The tool finally outputs the minimum eye width for both read and write eye diagrams, along with the minimum eye width limit value (selecting the closest frequency).

DDR DQ Minimum Eye Width Limits​

Based on DEMO testing and relevant project experience, this document sets corresponding limits for the minimum read/write eye width of DDR DQ. If the minimum read/write eye width does not meet this limit, DDR operation may be unstable.

Meeting the DDR DQ minimum eye width limit only indicates that the DDR DQ eye width is relatively reliable under the current design. It does not mean that the DDR-related design definitely has no other issues. Please conduct further reliability testing according to actual usage requirements.

RV1126 DDR DQ Minimum Eye Width Limit Values​

DDR TypeDDR Clock FrequencyMin Read Eye Width LimitMin Write Eye Width Limit
LPDDR41056MHz1213
LPDDR4924MHz1515
DDR41056MHz139
DDR4924MHz1511
LPDDR31056MHz1513
LPDDR3924MHz1615
DDR31056MHz1414
DDR3924MHz1717

RK356x DDR DQ Minimum Eye Width Limit Values​

DDR TypeDDR Clock FrequencyMin Read Eye Width LimitMin Write Eye Width Limit
LPDDR41560MHz2524
LPDDR41184MHz3029
DDR41560MHz3022
DDR41184MHz3226
LPDDR31184MHz3425
LPDDR31056MHz3928
DDR31184MHz3231
DDR31056MHz3934