Skip to main content

Understanding-Innosilicon-DDR-PHY

Rockchip

Understanding the Innosilicon DDR PHY

Release Version: 1.0

Author Email: typ@rock-chips.com

Date: 2017.12.04

Security Level: Internal

Preface

Provides a way for RK internal colleagues to understand the inno DDR PHY.

Product Version

Chip NameKernel Version
RK292x,RK3026,RK3028A,RK3036,RK312x,RK322x,RK322xH,RK3366,RK3368,RK1108,rk3326All kernel versions

Intended Audience RK internal engineers

Revision History

DateVersionAuthorChange Description
2017.12.04V1.0Tang Yunping

[TOC]​

PHY Versions Corresponding to Chips

PlatformVersion
RK3036/RK3026/RK3028A/RK3126B/CV2.62
RK3126/RK3128V2.63
RK3368V2.65
RK3366V2.66
RK3228V2.70
RV1108V2.72
RK3228H/RK3328V2.84

Functions the DDR PHY Needs to Implement

​ The DDR controller and the DDR PHY are connected through the DFI interface. The main function of the DDR PHY is to convert the various digital signals issued by the DDR controller into analog signals that the DDR particles can recognize, and to convert the analog signals issued by the DDR particles into DFI signals that the DDR controller can recognize. It is similar to analog-to-digital / digital-to-analog conversion. So it is mainly the forwarding of Command/Address and write signals, and the reception of read signals.

DLL

​ The DLL in the DDR PHY and the DLL in the DDR particles serve completely different purposes. The DLL in the DDR particles is mainly to make the ODT switching timing and tDQSCK more precise. The DDR PHY is mainly for precise phase control between CLK and CMD/ADDRESS, and between read/write DQS and DQ. The Inno DDR PHY DLL mainly consists of one MASTER DLL and 9 SLAVE DLLs: CMD/CLK share one SLAVE DLL, each group of write DQS/DQ shares one SLAVE DLL, and each group of read DQS/DQ shares one SLAVE DLL.

  1. Phase between CLK and CMD/ADDRESS

    1. For DDR3/DDR2/DDR4, the phase between CMD and CLK is 180°. This 180° is triggered directly by the 4x clk and does not require DLL involvement.
    2. For LPDDR2/LPDDR3, the 90° phase difference between CMD and CLK is achieved by a fixed 180° from the 4x clk plus the 90° generated by the CMD DLL. If it is in DLL bypass mode, the 90° phase difference is generated directly by the 4x clk.

  2. Phase between Write DQS and DQ

    1. In DLL normal mode, the 90° phase difference between write DQS and DQ is directly achieved by the DQS/DQ TX DLL.
    2. In DLL bypass mode (controlled by register address 0x290), the 90° is directly achieved by the 4x CLK. So inno's DLL bypass can also accurately achieve write phase control.
    3. Inno recommends that the Write DLL adjustment range should not exceed 67.5° to 112.5°. Otherwise instability may occur.

  3. Phase between Read DQS and DQ

    1. A 90° phase difference needs to be achieved between Read DQS and DQ. The phase difference between DQS and DQ consists of a fixed delay on the DQS path plus the DLL delay.

      The fixed delay on the DQS path, for a PHY that cannot run at 800M, is generally around 300ps; for a PHY that can run at 800M, it is around 150ps.

      Since the DQS has a fixed delay, the DLL setting needs to be determined according to the frequency: 0°, 22.5°, 45°, or 67.5°.

    2. The Read DLL cannot work in bypass mode.

  4. Viewing the Master DLL lock status

    Register address 0x3e4 bit[5:0]: DLL lock value. If it is all 0s or all 1s, it indicates the DLL is in the unlock state.

DQS gate calibration

​ Also known as Read gate training. In principle, the DQS/DQ pins of the DDR PHY are bidirectional, and DQS/DQ need to switch among Rx, Tx, and high-impedance states. The time from when a Read command is issued until the DQS/DQ data returns differs from board to board, so the DDR PHY needs to train out a definite window for each board to set the DQS/DQ pin to the Input state to sample the correct data. In other words, this DQS gate is a gate window during which the DDR PHY DQS/DQ pin is set to the Input state. When the Inno DDR PHY performs DQS gate calibration, it only samples the DQS signal and does not care whether the DQ data is correct. Therefore, the result of the Inno DDR PHY DQS gate calibration can only reflect the connectivity of DQS, but not the connectivity of DQ.

  1. DQS gate calibration for 292x, 302x, 312x, 3036

    By default, only the DQS of cs0 is trained and used as the gate result for all cs. It cannot train separately for each cs.

  2. DQS gate calibration for rk3368, rk3366, rk322x, rk1108, rk322xh

    ​ A function to train the two cs separately was added. Register address 0x8 bit[4:5] controls which cs is trained. However, this training has a bug.

    ​ If bit4-5 of the offset 0x8 address is set to 00, there are actually two training windows, one for cs0 and one for cs1. During actual access, the PHY will automatically switch between the cs0 window and the cs1 window. If bit4-5 is set to cs0 or cs1, only the window of the selected cs is used during operation, and the window is not switched according to cs. In fact, only the value of the last trained cs can be observed in the registers; the window value of the other cs trained previously cannot be known through the registers.

    ​ When training, if training cs0, the offset 0x8 address needs to be configured as 0x20->0x21->training->0x20->0x00. The same applies to cs1. If after training it switches directly from 0x21 or 0x11 to 0x0, a contention problem will occur. If only the cs0 training result is used and applied to all cs, you can do 0x20->0x21->training->0x20 to end the training. Similarly, for cs1 it is 0x10->0x11->training->0x10.

    ​ The two-cs training has the following bug: when the training results of the two cs differ by 1 on a 1xclk cycle, the gate needs a certain amount of time to switch between the two cs, so read-to-read in different rank needs additional cycles to avoid this problem.

  3. rk3368, rk3366, rk322x, rk1108, rk322xh DQS gate calibration bypass

    1. Register offset address 0x8 bit[1] set to 1 is bypass mode

      ADDRBITDEFAULTDESCRIPTIONS
      8'h2c[7:5]3'b001Use to control the cyc_dly of the left channels A for CS0.cyc_dly = CFG * 1x clock cycle.
      8'h2c[4:3]2'b11Use to control the oph_dly of the left channels A for CS0.oph_dly = CFG * 4x clock cycle.
      8'h2c[2:0]3'b100Use to control the dll_dly of the left channels A for CS0.dll_dly = CFG * DLL step.
      8'h2d[7:5]3'b001Use to control the cyc_dly of the left channels A for CS1.cyc_dly = CFG * 1x clock cycle.
      8'h2d[4:3]2'b11Use to control the oph_dly of the left channels A for CS1.oph_dly = CFG * 4x clock cycle.
      8'h2d[2:0]3'b100Use to control the dll_dly of the left channels A for CS1.dll_dly = CFG * DLL step.
      8'h3c[7:5]3'b001Use to control the cyc_dly of the right channels A for CS0.cyc_dly = CFG * 1x clock cycle.
      8'h3c[4:3]2'b11Use to control the oph_dly of the right channels A for CS0.oph_dly = CFG * 4x clock cycle.
      8'h3c[2:0]3'b100Use to control the dll_dly of the right channels A for CS0.dll_dly = CFG * DLL step.
      8'h3d[7:5]3'b001Use to control the cyc_dly of the right channels A for CS1.cyc_dly = CFG * 1x clock cycle.
      8'h3d[4:3]2'b11Use to control the oph_dly of the right channels A for CS1.oph_dly = CFG * 4x clock cycle.
      8'h3d[2:0]3'b100Use to control the dll_dly of the right channels A for CS1.dll_dly = CFG * DLL step.
      8'h4c[7:5]3'b001Use to control the cyc_dly of the left channels B for CS0.cyc_dly = CFG * 1x clock cycle.
      8'h4c[4:3]2'b11Use to control the oph_dly of the left channels B for CS0.oph_dly = CFG * 4x clock cycle.
      8'h4c[2:0]3'b100Use to control the dll_dly of the left channels B for CS0.dll_dly = CFG * DLL step.
      8'h4d[7:5]3'b001Use to control the cyc_dly of the left channels B for CS1.cyc_dly = CFG * 1x clock cycle.
      8'h4d[4:3]2'b11Use to control the oph_dly of the left channels B for CS1.oph_dly = CFG * 4x clock cycle.
      8'h4d[2:0]3'b100Use to control the dll_dly of the left channels B for CS1.dll_dly = CFG * DLL step.
      8'h5c[7:5]3'b001Use to control the cyc_dly of the right channels B for CS0.cyc_dly = CFG * 1x clock cycle.
      8'h5c[4:3]2'b11Use to control the oph_dly of the right channels B for CS0.oph_dly = CFG * 4x clock cycle.
      8'h5c[2:0]3'b100Use to control the dll_dly of the right channels B for CS0.dll_dly = CFG * DLL step.
      8'h5d[7:5]3'b001Use to control the cyc_dly of the right channels B for CS1.cyc_dly = CFG * 1x clock cycle.
      8'h5d[4:3]2'b11Use to control the oph_dly of the right channels B for CS1.oph_dly = CFG * 4x clock cycle.
      8'h5d[2:0]3'b100Use to control the dll_dly of the right channels B for CS1.dll_dly = CFG * DLL step.

VREF/RZQ

​ VREF: The VREF of the Inno DDR PHY is not pinned out; it is generated and used directly inside the PHY. And the method Inno previously provided to adjust VREF is actually ineffective. So the Inno DDR PHY VREF is internally generated and not adjustable.

​ RZQ: Hardened inside the PHY and not adjustable.

DFI lowpower function

​ A new feature of the rk322xh/rk3328 DDR PHY. After the DFILPCFG register in the controller is enabled, the controller will also put the PHY into a low_power state when entering pd_idle/sr_idle. At this time, the PHY will gate off unnecessary clocks to save power as much as possible.

​ Note that in DDR3/DDR4 power_down mode, the DDR CLK cannot be stopped, so the dfi lowpower function cannot be enabled under DDR3/DDR4 pd_idle.

​ PHY register offset 0x24 bit[6] can also directly bypass this low power function.

Test pin function

​ ODT0 can be used as a test pin to observe internal signals. The settings are as follows:

Set [1] of 0x40 to 1, enable the cmd-related obs signal Set [4] of 0x294 to 1, ODT0 becomes the test pin Set [3:0] of 0x294 to select different signals to send to ODT0 for observation, where: Set [3:0] of 0x294 to 0101 to observe the 4xclk before the cmd DLL Set [3:0] of 0x294 to 0110 to observe the 4xclk after the cmd DLL; the default is 0 degrees, and 90-degree and 135-degree signals can be observed by adjusting the cmd dll phase Set [3:0] of 0x294 to 1100 to observe the internal CK signal sent to the CK driver Set [3:0] of 0x294 to 1101 to observe the internal enb signal sent to the CK driver; this signal is low when CK is outputting normally

PHY soft reset

PHY register offset address 0, bit[2]: reset analog logic, bit[3]: reset digital core

For the Inno DDR PHY, when the frequency changes (that is, during frequency scaling), the analog and digital parts of the DDR PHY need to be reset again. This reset does not affect the register values. After reset, the analog part must be released first for at least 500 DFI CLK cycles to ensure DLL lock, and then the digital part can be released.

write leveling

DDR PHY versions after V2.65 have the WRLVL function. However, WRLVL achieves its function by adjusting de-skew, and the movable range of de-skew itself is not large, so it is of no practical significance to use. From the verification results of several current platforms, WRLVL also has some bugs and cannot be used.

Configure the offset 0x14, 0x18 registers to the MR1 value for which write leveling needs to be enabled, then configure the offset 0x8 register to enable write leveling, and check the offset 0x3c0 register to determine whether write leveling is complete. After write leveling is complete, configure the offset 0x8 register to stop write leveling, and manually send MR1 to let the DDR exit write leveling. ​ When there are two CS, jedec stipulates that when doing write leveling on one cs, the other cs must be set to output disable (MR1 bit12 set to 1). ​ Write leveling is similar to data training; you can choose which cs to perform write leveling on. The leveling result is shown in 0x3c4 and 0x3c8. This group of registers only shows the result of the last cs for which write leveling was performed. If Write leveling CS select signal is selected as cs0 and cs1, the write leveling value is actually switched internally when writing to each cs. In this case, per-bit de-skew cannot be used, and write leveling must be bypassed before per-bit de-skew can be used.

de-skew

  1. The de-skew function consists of delay elements connected in series on the signal lines inside the PHY. By controlling the number of delay elements connected in series on each signal line through the de-skew register, the delay of each signal line can be changed.

  2. For the TX part of differential signals such as CLK and DQS, there are two registers that can adjust the delay of the positive and negative lines separately. The RX part de-skew is connected after the differential amplifier, so the RX part of the differential signal has only one register for adjustment.

  3. For DDR PHY versions after V2.65 that support WRLVL, since WRLVL is also implemented using the de-skew function, to manually change the de-skew, WRLVL must be bypassed before the de-skew set by the register takes effect. All DQS/DQ TX and RX can be set to different values separately for the two cs.

  4. Problems with de-skew:

    Since for versions after V2.65 the RX de-skew has two groups of de-skew for the two cs, Inno has design flaws in the switching timing of the rx de-skew between the two cs: 1. The switching time point is incorrect; some signals switch earlier and some later, and the maximum time difference can be up to 800ps. 2. The switching circuit has glitches. This causes signal sampling errors during reads when switching between the two cs due to the rx de-skew switching problem. There are three ways to avoid this problem:

    1. Set the rx de-skew switching timing according to the read gate training result, and control the rx de-skew switching timing within the diff_cs_rd_gap interval.
    2. Set rx de-skew not to switch on the register, and use the de-skew value of one cs for both cs, so there is no switching problem. 0x270 bit[0:1] controls which cs's de-skew is used. 00: both cs0 and cs1 use it; 01: only cs1's de-skew is used; 02: only cs0's de-skew is used.
    3. Increase diff_cs_rd_gap in the DDR controller.