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Pin Definition

The X3128BV3 uses the X3128CV4 144-pin castellated core board. The tables below list pins 1 to 144.

Core Board Pin Definition 1​

Pin No.SignalDescription
1VCC_SYSCore-board main power output, 4.2V
2CIF_PDN0GPIO3_D7, general-purpose GPIO
3PWM0GPIO0_D2,muxed as PWM0
4PWM1GPIO0_D3,muxed as PWM1
5PWM2GPIO0_D4,muxed as PWM2
6UART0_RTSGPIO0_C1,muxed as UART0
7UART0_RXDGPIO2_D3,muxed as UART0
8UART0_CTSGPIO2_D5,muxed as UART0
9UART0_TXDGPIO2_D2,muxed as UART0
10IR_RXGPIO3_D2, muxed as infrared receiving port
11SPDIF_TXGPIO3_D3, muxed as fiber output
12TX_C-HDMI differential pair
13TX_C+HDMI differential pair
14TX_0-HDMI differential pair
15TX_0+HDMI differential pair
16TX_1-HDMI differential pair
17TX_1+HDMI differential pair
18TX_2-HDMI differential pair
19TX_2+HDMI differential pair
20VDAC_OUTPDAC output
21OTG_IDOTG ID pin
22OTG_DETOTG detect pin
23HOST_DPHOST differential pair
24HOST_DMHOST differential pair
25OTG_DPOTG differential pair
26OTG_DMOTG differential pair
27SDMMC_DETSDMMC0 pin group
28SDMMC_CMDSDMMC0 pin group
29SDMMC_D0SDMMC0 pin group
30SDMMC_D1SDMMC0 pin group
31SDMMC_D2SDMMC0 pin group
32SDMMC_D3SDMMC0 pin group
33SDMMC_CLKSDMMC0 pin group
34I2C3_SDAGPIO0_A7,muxed as I2C3_SDA
35I2C3_SCLGPIO0_A6,muxed as I2C3_SCL
36VCC_IO3.3V DC-DC output

Core Board Pin Definition 2​

Pin No.SignalDescription
37VCC_IO3.3V DC-DC output
38HDMI_HPDGPIO0_B7,muxed as HDMI
39HDMI_CECGPIO0_C4,muxed as HDMI1
40UART1_TXGPIO1_B1,muxed as UART1
41UART1_RXGPIO1_B2,muxed as UART1
42UART1_RTSGPIO1_B3,muxed as UART1
43SPI_CLKGPIO0_B1,muxed as SPI
44SPI_CSn0GPIO0_B6,muxed as SPI
45SPI_TXDGPIO0_B3,muxed as SPI
46SPI_RXDGPIO0_B5,muxed as SPI
47SPI_CSn1GPIO1_B4,muxed as SPI
48SDMMC1_CLKSDMMC1 data group
49SDMMC1_D3SDMMC1 data group
50SDMMC1_D2SDMMC1 data group
51SDMMC1_D1SDMMC1 data group
52SDMMC1_D0SDMMC1 data group
53SDMMC_PWRSDMMC1 data group
54I2C1_SDA/SDMMC1_CMDSDMMC1 data group,muxed as I2C1
55I2C1_SCLGPIO0_A2,muxed as I2C1
56I2C0_SCLGPIO0_A0,muxed as I2C0
57I2C0_SDAGPIO0_A1,muxed as I2C0
58GSENSOR_INTGPIO0_B4, muxed as I2S interface
59TP_INTGPIO1_B0,muxed as UART1
60SPK_CTLGPIO0_D6, general-purpose GPIO
61TP_RSTGPIO0_D1, utilizing UART2
62HP_CTLGPIO3_C4, general-purpose GPIO
63LCD_RSTGPIO0_D0,muxed as UART2
64GPIO3_C7GPIO3_C7, general-purpose GPIO
65GPIO1_C7GPIO1_C7, general-purpose GPIO
66GPIO2_A2GPIO2_A2, general-purpose GPIO
67GPIO1_A7GPIO1_A7, general-purpose GPIO
68GPIO2_A0GPIO2_A0,muxed as SPI
69GPIO2_A1GPIO2_A1, general-purpose GPIO
70GPIO0_C7GPIO0_C7, general-purpose GPIO
71GPIO2_A6GPIO2_A6, general-purpose GPIO
72GNDGND

Core Board Pin Definition 3​

Pin No.SignalDescription
73GNDGround
74GPIO2_A4GPIO2_A4, general-purpose GPIO
75GPIO3_C6GPIO3_C6, general-purpose GPIO
76GPIO2_A3GPIO2_A3, general-purpose GPIO
77GPIO1_A3GPIO1_A3,muxed as I2S
78GPIO3_C5GPIO3_C5, general-purpose GPIO
79CODEC_AOLAudio output
80CODEC_AORAudio output
81MICBIASMIC bias
82MICIN-PAudio input
83MICIN-NAudio input
84HP_DETHeadphone detect pin
85LCD_D23GPIO2_D1,muxed as LCD,MAC
86LCD_D22GPIO2_D0,muxed as LCD,MAC
87LCD_D21GPIO2_C7,muxed as LCD,MAC
88LCD_D20GPIO2_C6,muxed as LCD,MAC
89I2C2_SCL_LCD_19GPIO2_C5,muxed as LCD,MAC,I2C2
90I2C2_SDA_LCD_18GPIO2_C4,muxed as LCD,MAC,I2C2
91LCD_D17GPIO2_C3,muxed as LCD,MAC
92LCD_D16GPIO2_C2,muxed as LCD,MAC
93LCD_D15GPIO2_C1,muxed as LCD,MAC
94LCD_D14GPIO2_C0,muxed as LCD,MAC
95LCD_D13GPIO2_B7,muxed as LCD,MAC
96LCD_D12GPIO2_B6,muxed as LCD,MAC
97LCD_D11GPIO2_B5,muxed as LCD,MAC
98LCD_D10GPIO2_B4,muxed as LCD,MAC
99LCD_D9muxed as RGB, LVDS, MIPI port, cannot be used as independent GPIO
100LCD_D8muxed as RGB, LVDS, MIPI port, cannot be used as independent GPIO
101LCD_D7muxed as RGB, LVDS, MIPI port, cannot be used as independent GPIO
102LCD_D6muxed as RGB, LVDS, MIPI port, cannot be used as independent GPIO
103LCD_D5muxed as RGB, LVDS, MIPI port, cannot be used as independent GPIO
104LCD_D4muxed as RGB, LVDS, MIPI port, cannot be used as independent GPIO
105LCD_D3muxed as RGB, LVDS, MIPI port, cannot be used as independent GPIO
106LCD_D2muxed as RGB, LVDS, MIPI port, cannot be used as independent GPIO
107LCD_D1muxed as RGB, LVDS, MIPI port, cannot be used as independent GPIO
108LCD_D0muxed as RGB, LVDS, MIPI port, cannot be used as independent GPIO

Core Board Pin Definition 4​

Pin No.SignalDescription
109GNDGround
110GNDGround
111LCD_HSYNCGPIO2_B1,muxed as LCD
112LCD_VSYNCGPIO2_B2,muxed as LCD
113LCD_CLKGPIO2_B0,muxed as LCD
114LCD_DENGPIO2_B3,muxed as LCD
115VCC_RK816INCore board power input, 4.8 to 5.5V
116VCC_RK816INCore board power input, 4.8 to 5.5V
117VCC_RK816INCore board power input, 4.8 to 5.5V
118PWRONPMU power-on pin, active low
119VCC_RTCRTC power input pin, 3V
120BAT_PBattery input pin
121BAT_NBattery input pin
122RTC_CLKOUT32768Hz clock output
123VCC28_CIFPMU LDO1 output, adjustable voltage
124VCC18_CIFPMU LDO2 output, adjustable voltage
125VCC_TPPMU LDO6 output, adjustable voltage
126VCCA_CODECPMU LDO5 output, adjustable voltage
127RESETCPU reset pin, active low
128ADCIN2ADC input pin, 3.3V reference
129ADCIN1ADC input pin, 3.3V reference
130ADCIN0ADC input pin, 3.3V reference
131CIF_CLKOUTBT656 / BT601 camera data signal, cannot be used as normal GPIO
132CIF_CLKINBT656 / BT601 camera data signal, cannot be used as normal GPIO
133CIF_HREFBT656 / BT601 camera data signal, cannot be used as normal GPIO
134CIF_VSYNCBT656 / BT601 camera data signal, cannot be used as normal GPIO
135CIF_D7BT656 / BT601 camera data signal, cannot be used as normal GPIO
136CIF_D6BT656 / BT601 camera data signal, cannot be used as normal GPIO
137CIF_D5 /BT656 / BT601 camera data signal, cannot be used as normal GPIO
138CIF_D4BT656 / BT601 camera data signal, cannot be used as normal GPIO
139CIF_D3BT656 / BT601 camera data signal, cannot be used as normal GPIO
140CIF_D2BT656 / BT601 camera data signal, cannot be used as normal GPIO
141CIF_D1BT656 / BT601 camera data signal, cannot be used as normal GPIO
142CIF_D0BT656 / BT601 camera data signal, cannot be used as normal GPIO
143CIF_PDN1GPIO3_D7, general-purpose GPIO
144VCC_SYSCore-board main power output