Pin Definition
Pin Definition
Core BoardPin Definition1
Core BoardPin Definition1
| Pin No. | Signal | Type | Description |
|---|---|---|---|
| 1 | TX_C+ | HDMI TX1.4 differential pair | Cannot be used as GPIO |
| 2 | TX_C- | HDMI TX1.4 differential pair | Cannot be used as GPIO |
| 3 | TX_0+ | HDMI TX1.4 differential pair | Cannot be used as GPIO |
| 4 | TX_0- | HDMI TX1.4 differential pair | Cannot be used as GPIO |
| 5 | TX_1+ | HDMI TX1.4 differential pair | Cannot be used as GPIO |
| 6 | TX_1- | HDMI TX1.4 differential pair | Cannot be used as GPIO |
| 7 | TX_2+ | HDMI TX1.4 differential pair | Cannot be used as GPIO |
| 8 | TX_2- | HDMI TX1.4 differential pair | Cannot be used as GPIO |
| 9 | VDAC_OUTP | Digital-to-analog conversion output | Cannot be used as GPIO |
| 10 | OTG_ID | OTG_ID identification pin | Cannot be used as GPIO |
| 11 | OTG_DET | OTG_DET identification pin | Cannot be used as GPIO |
| 12 | HOST_DM | USB 2.0 differential pair | Cannot be used as GPIO |
| 13 | HOST_DP | USB 2.0 differential pair | Cannot be used as GPIO |
| 14 | OTG_DM | USB 2.0_OTG differential pair | Cannot be used as GPIO |
| 15 | OTG_DP | USB 2.0_OTG differential pair | Cannot be used as GPIO |
| 16 | UART0_RXD(GPIO2_D3/CARD_CLK/UART0_RX_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 17 | UART0_TXD(GPIO2_D2/CARD_RST/UART0_TX_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 18 | UART0_RTS(GPIO0_C1/CARD_IO/UART0_RTSN_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 19 | UART0_CTS(GPIO2_D5/CARD_DET/UART0_CTSN_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 20 | IR_RX(GPIO3_D2/IR_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 21 | PWM0(GPIO0_D2/PWM0_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 22 | SPDIF_TX(GPIO3_D3/SPDIF_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 23 | ADCIN1 | ADCINinput | Cannot be used as GPIO |
| 24 | GND | ReferenceGround | |
| 25 | GND | ReferenceGround | |
| 26 | SDMMC_D0(GPIO1_C2/SDMMC0_D0/UART2_TX_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 27 | SDMMC_D1(GPIO1_C3/SDMMC0_D1/UART2_RX_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 28 | SDMMC1_D3(GPIO1_A5/I2S_SDI/SDMMC1_D3_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU |
Core BoardPin Definition2
Core BoardPin Definition2
| Pin No. | Signal | Type | Description |
|---|---|---|---|
| 29 | SDMMC1_D2(GPIO1_A4/I2S_SDO/SDMMC1_D2_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 30 | SDMMC1_D1(GPIO1_A2/I2S_LRCK_RX/SDMMC1_D1_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 31 | SDMMC1_D0(GPIO1_A1/I2S_SCLK/SDMMC1_D0/PMIC_SLEEP_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 32 | SDMMC1_CLK(GPIO1_A0/I2S_MCLK/SDMMC1_CLKO/XIN_32K_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 33 | GSENSOR_INT(GPIO0_B4/I2S_LRCK_TX_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 34 | WIFI_PWR(GPIO1_A3/I2S_LRCK_TX_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 35 | HDMI_HPD(GPIO0_B7/HDMI_HPD_d) | GPIOmuxed as pin, the level is determined by the HDMI driver level (3.3V) | |
| 36 | HDMI_CEC(GPIO0_C4/HDMI_CEC_u) | GPIOmuxed as pin, the level is determined by the HDMI driver level (3.3V) | |
| 37 | I2C1_SCL(GPIO0_A2/I2C1_SCL_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 38 | I2C1_SDA/SDMMC1_CMD(GPIO0_A3/I2C1_SDA/SDMMC1_CMD_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 39 | I2C3_SDA(GPIO0_A7/HDMI_SDA/I2C3_SDA_u) | GPIOmuxed as pin, the level is determined by the HDMI driver level (3.3V) | |
| 40 | I2C3_SCL(GPIO0_A6/HDMI_SCL/I2C3_SCL_u) | GPIOmuxed as pin, the level is determined by the HDMI driver level (3.3V) | |
| 41 | UART1_RX(GPIO1_B2/UART1_RX/SPI_RXD_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 42 | UART1_TX(GPIO1_B1/UART1_TX/SPI_TXD_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 43 | RESET | reset pin | Cannot be used as GPIO |
| 44 | PWRON | power pin | Cannot be used as GPIO |
| 45 | RTC_CLKOUT | RTC clock output(32.768Khz) | Cannot be used as GPIO |
| 46 | I2C0_SDA(GPIO0_A1/I2C0_SDA_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 47 | I2C0_SCL(GPIO0_A0/I2C0_SCL_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 48 | GND | ReferenceGround | Cannot be used as GPIO |
| 49 | GND | ReferenceGround | Cannot be used as GPIO |
| 50 | VCC28_CIF | 2.8V power supply | Cannot be used as GPIO |
| 51 | VCC18_CIF | 1.8V power supply | Cannot be used as GPIO |
| 52 | VCCA_CODEC | audio power supply | |
| 53 | VCC_SYS | Core-board main power output，4.2V | Cannot be used as GPIO |
| 54 | VCC_SYS | Core-board main power output，4.2V | Cannot be used as GPIO |
| 55 | VCC_TP | TP power supply | Cannot be used as GPIO |
| 56 | VCC_RTC | RTCpower supplypin，3Vinput | Cannot be used as GPIO |
Core BoardPin Definition3
Core BoardPin Definition3
| Pin No. | Signal | Type | Description |
|---|---|---|---|
| 57 | BAT_N | Battery input pin | Cannot be used as GPIO |
| 58 | BAT_P | Battery input pin | Cannot be used as GPIO |
| 59 | VCC_RK816IN | Core BoardPower input, 4.8 to 5.5V | Cannot be used as GPIO |
| 60 | VCC_RK816IN | Core BoardPower input, 4.8 to 5.5V | Cannot be used as GPIO |
| 61 | VCC_RK816IN | Core BoardPower input, 4.8 to 5.5V | Cannot be used as GPIO |
| 62 | VCC_IO | 3.3V DC-DCoutput | Cannot be used as GPIO |
| 63 | VCC_IO | 3.3V DC-DCoutput | Cannot be used as GPIO |
| 64 | TP_INT(GPIO1_B0/UART1_CTSN/SPI_CLK_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 65 | TP_RST(GPIO0_D1/UART2_CTSN_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 66 | HP_CTL(GPIO3_C4_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 67 | LCD_RST(GPIO0_D0/UART2_RTSN/PMIC_SLEEP_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 68 | GPIO3_C6 | GPIOpin, the level is determined by the level of the program control PMU | |
| 69 | SPI_CLK(GPIO0_B1/I2S_SCLK/SPI_CLK_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 70 | SPI_TXD(GPIO0_B3/I2S_LRCK_RX/SPI_TXD_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 71 | SPI_RXD(GPIO0_B5/I2S_SDO/SPI_RXD_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 72 | SPI_CSn0(GPIO0_B6/I2S_SDI/SPI_CSN0_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 73 | GPIO1_C7(GPIO1_C7/FLASH_CS3/eMMC_RST_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 74 | CIF_PDN0(GPIO3_D7/CIF_PDN0/TEST_CLKO_d) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 75 | GPIO0_C7(GPIO0_C7/FLASH_CS1_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 76 | GPIO2_A6(GPIO2_A6/FLASH_CS0_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 77 | GPIO2_A4(GPIO2_A4/FLASH_RDY/eMMC_CMD/SFC_CLK_u) | GPIOmuxed as pin, the level is determined by the level of the program-controlled PMU | |
| 78 | GPIO3_C5 | GPIOpin, the level is determined by the level of the program control PMU | |
| 79 | MICBIAS | MIC bias | Cannot be used as GPIO |
| 80 | CODEC_AOL | audiooutput interface | Cannot be used as GPIO |
| 81 | CODEC_AOR | audiooutput interface | Cannot be used as GPIO |
| 82 | MICIN-P | MICoutput interface | Cannot be used as GPIO |
| 83 | MICIN-N | MICoutput interface | Cannot be used as GPIO |
| 84 | HP_DET | Headphone detection pin | Cannot be used as GPIO |
Core BoardPin Definition4
Core BoardPin Definition4
| Pin No. | Signal | Type | Description |
|---|---|---|---|
| 85 | LCD_CLK(GPIO2_B0/LCDC_CLK/EBC_SDCLK/GMAC_RXDV_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | |
| 86 | LCD_DEN(GPIO2_B3/LCDC_DEN/EBC_GDCLK/GMAC_RXCLK_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | |
| 87 | LCD_HSYNC(GPIO2_B1/LCDC_HSYNC/EBC_SDLE/GMAC_TXCLK_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | |
| 88 | LCD_VSYNC(GPIO2_B2/LCDC_VSYNC/EBC_SDOE/GMAC_CRS_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | |
| 89 | LCD_D23(GPIO2_D1/LCDC_D23/EBC_GDPWR2/GMAC_MDC_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 90 | LCD_D22(GPIO2_D0/LCDC_D22/EBC_GDPWR1/GPS_CLK/GMAC_COL_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 91 | LCD_D21(GPIO2_C7/LCDC_D21/EBC_BORDER1/GPS_MAG/GMAC_TXD3_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 92 | LCD_D20(GPIO2_C6/LCDC_D20/EBC_BORDER0/GPS_SIGN/GMAC_TXD2_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 93 | I2C2_SCL_LCD_19(GPIO2_C5/LCDC_D19/EBC_SDSHR/I2C2_SCL/GMAC_RXD2_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 94 | I2C2_SDA_LCD_18(GPIO2_C4/LCDC_D18/EBC_GDRL/I2C2_SDA/GMAC_RXD3_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 95 | LCD_D17(GPIO2_C3/LCDC_D17/EBC_GDPWR0/GMAC_TXD0_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 96 | LCD_D16(GPIO2_C2/LCDC_D16/EBC_GDSP/GMAC_TXD1_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 97 | LCD_D15(GPIO2_C1/LCDC_D15/EBC_GDOE/GMAC_RXD0_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 98 | LCD_D14(GPIO2_C0/LCDC_D14/EBC_VCOM/GMAC_RXD1_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 99 | LCD_D13(GPIO2_B7/LCDC_D13/EBC_SDCE5/GMAC_RXER_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 100 | LCD_D12(GPIO2_B6/LCDC_D12/EBC_SDCE4/GMAC_CLK_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 101 | LCD_D11(GPIO2_B5/LCDC_D11/EBC_SDCE3/GMAC_TXEN_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 102 | LCD_D10(GPIO2_B4/LCDC_D10/EBC_SDCE2/GMAC_MDIO_d) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 103 | LCD_D9(LCDC_D9/LVDS_CLKN/EBC_SDCE1/MIPI_CLKN) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 104 | LCD_D8(LCDC_D8/LVDS_CLKP/EBC_SDCE0/MIPI_CLKP) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 105 | LCD_D7(LCDC_D7/LVDS_TX3N/EBC_SDDO7/MIPI_D3N) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 106 | LCD_D6(LCDC_D6/LVDS_TX3P/EBC_SDDO6/MIPI_D3P) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 107 | LCD_D5(LCDC_D5/LVDS_TX2N/EBC_SDDO5/MIPI_D2N) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 108 | LCD_D4(LCDC_D4/LVDS_TX2P/EBC_SDDO4/MIPI_D2P) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 109 | LCD_D3(LCDC_D3/LVDS_TX1N/EBC_SDDO3/MIPI_D1N) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 110 | LCD_D2(LCDC_D2/LVDS_TX1P/EBC_SDDO2/MIPI_D1P) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 111 | LCD_D1(LCDC_D1/LVDS_TX0N/EBC_SDDO1/MIPI_D0N) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |
| 112 | LCD_D0(LCDC_D0/LVDS_TX0P/EBC_SDDO0/MIPI_D0P) | LCDC/LVDS/MIPI/GMAC/EMACmuxed as interface, the level is determined by VCCIO | Cannot be used as GPIO |